Since the bipartisan CHIPS and Science Act was signed into law in August 2022, the Commerce Department’s National Institute of Standards and Technology (NIST) has hit the ground running to reach its goal of the United States being the only country in the world that invents, designs, manufactures, and packages leading edge chips by 2030.
According to NIST Director Laurie Locascio, in just two years, CHIPS research and development (R&D) programs have proposed over $8 billion in R&D initiatives to help reach that goal.
“That includes more than $5 billion in the NSTC [National Semiconductor Technology Center] and more than $3 billion in the NAPMP [National Advanced Packaging Manufacturing Program],” Locascio said during an ITI webinar today. “Also, more than $285 million in the CHIPS Manufacturing USA Institute around digital twins and $54 million for small business innovation research – we’ll be announcing those grants soon – and $130 million in CHIPS metrology projects. Lots going on.”
Locascio highlighted NIST’s announcement earlier this summer on the three new facilities for advanced semiconductor R&D within NSTC: Prototyping and NAPMP Advanced Packaging Piloting Facility; Administrative and Design Facility; and Extreme Ultraviolet Center.
“These three facilities, they are going to be these centers of energy, these places where people convene, where the members come to do joint research and to do their best research, and we think this is going to be the best way to serve the entire country through these three facilities,” Locascio said.
“When these three facilities are operational, they’re going to be these world class destinations,” she said. “We’re very well underway into establishing these places, these place-based centers of excellence for the United States and semiconductor research. And you’re going to see a lot of exciting news coming out in the coming months regarding these facilities.”
Locascio highlighted that NIST’s CHIPS R&D initiatives – NSTC; NAPMP; Manufacturing USA; and CHIPS metrology – are four distinct programs but they’re designed to be working together and in tandem.
“We have designed connections between all of these four programs,” Locascio said. “We genuinely do not believe that creating four distinct programs that are all separate and don’t work together will accomplish the bold vision that we have and will achieve the goals for the country.”
“Notably and very importantly, very recently, we announced our facilities plan,” she said. “We announced our intent to co-locate the NSTC R&D prototyping facility and the advanced packaging piloting facility. These are huge investments. These are the largest investments in NSTC and NAPMP, and we are building a hard link between these two programs by physically connecting our major investments in each of these programs.”
“There’s a reason for that, because we really wanted to enable world class research across the full technology stack for semiconductors, from materials to design to manufacturing to packaging,” Locascio said. “And the reason why this is really important is because the lines today between chip design and packaging are really blurred … especially in critical application areas like chips for AI, the lines between the chip and package are becoming seamless. So that’s our first investment that really created this hard link, and you’re going to see more of that coming out this fall.”
The metrology program is built to feed directly into the NSTC and NAPMP, Locascio said.
“As we’re developing new tools, for instance, for measuring atomic scale devices with three dimensional features, we plan to have these tools and have that data available for the NSTC and the NAPMP facility,” she said. “This is really built and designed to be all intertwined and connected to take advantage of the capabilities that we’re building.”
Lastly, Locascio said the digital twin Manufacturing USA Institute was designed with a direct linkage to the NSTC and NAPMP programs to be a “collaborative space to validate and verify some of the models.”
“We’ve taken the past year to really design these programs and design the connections between the programs so that in some they really cover all of the major R&D gaps that industry faces,” Locascio said. “We’ve listened, we’ve heard industry, and we’re designing these very deliberately. And the programs together build out complementary resources and directly work with each other. So, the planning is done.”
“We’re at the point where [we’ve got] the right projects and the right partners to act out our plans, and that’s critical,” she added. “We have to have our partners and projects that are open and collaborative, that have transformational ideas and the right mindset for public-private partnership, because that’s what it’s all about.”
Workforce is another critical piece to achieving semiconductor dominance in the U.S. by 2030, and Locascio teased that NSTC will be announcing a workforce center of excellence soon.
“We have a number of investments … to support workforce development, workforce curricula, trying to draw in new people who never thought of the semiconductor industry before, to attract them into this industry and a place where they can have a really great job to support their families and to support the local and regional economies that we’re building around the United States with these investments,” she said.
The NIST leader said it will be an “aggressive fall” as her team prepares to announce more opportunities for industry to advance the country’s semiconductor sector – including a forthcoming $1.6 billion in funding from the NAPMP.
